The present invention relates to a semiconductor design technique, and more particularly, to an internal source voltage generation circuit and a generation method thereof.
An internal source voltage generation circuit may be mounted on a semiconductor memory device such as a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The semiconductor memory device uses internal source voltages which are generated by the internal source voltage generation circuit and have various voltage levels, and may thus be ensured with efficient power consumption and stable circuit operations. The internal source voltages include a core source voltage and a peripheral source voltage which are generated by down-converting an external source voltage and a pumping source voltage and a substrate bias source voltage, which are generated by pumping the external source voltage and a ground source voltage. The internal structure of the semiconductor memory device is divided into a core region and a peripheral region. The core source voltage is a source voltage that is applied to a circuit located in the core region, and the peripheral source voltage is a source voltage that is applied to a circuit located in the peripheral region, hereinafter referred to as a peripheral circuit.
As semiconductor memory devices are becoming more highly integrated, manufacturing processes that allow them to have dimensions below a sub-micron level are being adopted when designing internal circuits, and at the same time, the operation frequencies of the semiconductor memory devices are gradually increasing. Also, in line with these changes in the semiconductor memory devices, the levels of external source voltages and internal source voltages used in the semiconductor memory devices are gradually decreasing. These changes may lead problems unseen in conventional semiconductor memory devices.
First, in a read operation of a semiconductor memory device, the data stored in a core region are transmitted to a pad through a global input/output line (GIO), which are produced in the semiconductor memory device and are then outputted to an outside, and in a write operation of the semiconductor memory device, the data inputted from the pad are transmitted to the core region through the global input/output line and are then stored. In other words, during the read and write operations of the semiconductor memory device, toggling operations occur on the global input/output line for transmitting data.
Since the global input/output line usually has a relatively large load, a circuit for driving the global input/output line should also have relatively large current driving capacity. Hereafter, for illustration purposes, a circuit for driving the global input/output line during the read operation of the semiconductor memory device is referred to as a ‘read driving section’, and a circuit for driving the global input/output line in the write operation of the semiconductor memory device is referred to as a ‘write driving section’. The read driving section and the write driving section should have large current driving capacity in order to drive the global input/output line having a large load.
The read driving section and the write driving section are included in a peripheral circuit and drive the global input/output line by receiving a peripheral source voltage. Therefore, as the read driving section and the write driving section having large current driving capacity operate during the read and write operations, the peripheral source voltage applied thereto is likely to drop. If the peripheral source voltage drops, stable operations of the read driving section and the write driving section may not be ensured, which means that data may not be properly transmitted to the global input/output line. Furthermore, a problem occurs in that the reliability of the semiconductor memory device deteriorates.